1. The Field of the Invention
The present invention relates a cell interface, comprises: anode of the first diode D1 connected together cathode of the third diode D3 form a first terminal, the anode of the fourth diode D4 connected together cathode of the second diode D2 form a second terminal, and the external positive voltage terminal VP connected between cathode of the first diode D1 and anode of the third diode D2, and connected between anode of the third diode D3 and cathode of the fourth diode D4 form a third terminal, the first terminal connected to a positive voltage terminal of first cell E1, the second terminal connected to a positive voltage terminal of second cell E2, the third terminal is external positive voltage terminal VP, can be not occur loop current in cells parallel circuit.
2. Description of Related Art
FIG. 1 shows a schematic diagram of a prior art circuit. The first cell EA and second cell EB uses conventional parallel circuit. Such scheme comes with the following drawbacks:    1. When operation of charge of the first cell E1 and second cell E2, can be occur loop current between the first cell E1 and second cell E2, form a power consumption.    2. When operation of discharge of the first cell E1 and second cell E2, can be occur loop current between the first cell E1 and second cell E2, form a power consumption.    3. When operation of no load of the first cell E1 and second cell E2, can be occur loop current between the first cell E1 and second cell E2, form a power consumption.